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rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a ADSST-MELODY-32 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 rev. a reference block diagram s/pdif r x codec ( ad183x) host melody 32 sram (optional) boot flash 512k 8, 100ns spi bus melody 32 audio processor general description the melody 32 family of digital audio decoders provides flexible solutions to the av receiver and dvd market. the solutions offered can be tailored to the exact needs of the application. combined with a range of high performance codecs from analog devices, the melody family becomes a comprehensive answer to the needs of the high quality digital audio market. the single-chip melody 32 combines a high performance dsp architecture (three computational units, two data address gener- ators, and a program sequencer) with two spi compatible ports, three serial ports, one uart port, a dma controller, three program- mable tim ers, general-purpose programmable flag pins, interrupt capabilities, and on-chip program and data memory spaces. the melody 32 integrates 64 k words of on-chip memory con- figured as 32 k words (24-bit) of program ram and 32 k words (16-bit) of data ram. power-down circuitry is also provided to meet the low power needs of battery-operated portable equipment. fabri- cated in a high speed, low power cmos process, the melody 32 operates with a 6.25 ns instruction cycle time (160 mips). all instructions, except two multiword instructions, can execute in a single cycle. features single-chip dsp-based implementation of digital audio algorithms up to 160 mips and extensive on-chip memory caters to a wide variety of applications 32-bit fixed point implementation from end to end pseudo floating point implementation and selective 48-bit fixed point implementation where necessary to improve sonic quality some of the applicable software solutions available are: dolby digital dolby pro logic ii dts es dts neo:6 mpeg aac multichannel thx surround ex srs circle surround ii 96 khz processing adi surround fields speaker enhancement bass/delay management automatic stream detection and code loading customer specific dsp modes host communication using spi flexible serial ports i 2 s support sram support support for iec60958 melody is a registered trademark of analog devices, inc. dts is a registered trademark, dts es and dts neo:6 are trademarks of digital theater systems, inc. thx is a registered trademark of thx ltd. thx surround ex is a jointly developed technology of thx ltd. and dolby laboratories, inc. srs and circle surround ii are trademarks of srs labs, inc. dolby and pro logic are registered trademarks of dolby laboratories. spi is a registered trademark of motorola.
rev a e2e ADSST-MELODY-32especifications parameter description min max unit v ddint internal (core) supply voltage 2.37 2.63 v v ddext external (i/o) supply voltage 2.97 3.63 v v ih1 high level input voltage 1 @ v ddint = max 2.0 v ddext v v ddext = max v ih2 high level input voltage 2 @ v ddint = max 2.2 v ddext v v ddext = max v il low level input voltage 1 @ v ddint = min e0.3 +0.8 v v ddext = min t amb ambient operating temperature 0 70 = = = = = = = = = = = = = = = = () () = () = = ( ) = = () () = = = = hrd hwr cp0 hcms hcioms br ts0 ts1ts2mosi0rs0rs1rs2mosi1opmodebmode1 0tmstditcdt2miso0dr0dr1dr2miso1tc0tc1 tc2sc0rc0rc1rc2sc1 reset trst 2 ci 3 dt10ddr210hd10 ms3C0 ioms rd wr couthcp0tmr20 bgh bg dt0 dt1dt2miso0tc0tc1tc2sc0rc0rc1rc2sc1ts0ts1ts2mosi0rs0rs1rs2mosi1 bms tdo td emu dr2miso1 c br hcms hcioms hd1he hrd hwr cidr0dr1bpssrdhcp bmode0bmode1opmodebpsstctmstdireset trst dt10ddr210 ms3C0 rd wr p0 bms ioms tsxrsxtdo emu tcxrcxdtxhdi0tmr20 im32xidepd tc ddit 2t mb 2 = =
rev a ADSST-MELODY-32 e3e warning! esd sensitive device caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADSST-MELODY-32 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. absolute maximum ratings * v ddint internal (core) supply voltage . . . . . e0.3 v to +3.0 v v ddext external (i/o) supply voltage . . . . . e0.3 v to +4.6 v v il ev ih input voltage . . . . . . . . . . . e0.5 v to v ddext + 0.5 v v ol ev oh output voltage swing . . . e0.5 v to v ddext + 0.5 v c l load capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . 200 pf t cclk core clock period . . . . . . . . . . . . . . . . . . . . . . . 6.25 ns f cclk core clock frequency . . . . . . . . . . . . . . . . . . 160 mhz t hclk peripheral clock period . . . . . . . . . . . . . . . . . . . 12.5 ns f hclk peripheral clock frequency . . . . . . . . . . . . . . . 80 mhz t store storage temperature range . . . . . . e65 + ( ) ()
rev a ADSST-MELODY-32 e4e pin configuration 104 105 107 102 103 100 101 108 106 99 98 93 94 95 96 91 92 90 88 89 97 87 85 86 83 84 81 82 79 80 78 74 75 76 77 73 11 10 16 15 14 13 18 17 20 19 22 21 12 24 23 26 25 28 27 30 29 34 33 32 31 36 35 5 4 3 2 7 6 9 8 1 38 39 40 41 42 44 45 46 47 48 49 50 51 52 53 54 55 56 37 43 72 71 70 69 68 67 66 65 64 63 61 60 59 58 57 62 pin 1 identifier top view (not to scale) d14 d15 had0 had1 gnd gnd had16 gnd hrd hwr gd 0 1 2 hd2 hd3 hd hd hd hd hd hd hd10 hd11 hd12 hd13 hd1 hd1 he d13 ms3 ms1 ioms bms br bg bgh 21 ddet ddit ms0 ddet ms2 gd t ci d c d12 d11 d10 d d d d d ddet gd d3 d2 d1 d0 rd wr cout 3 rs0 tc1 dr1 rc1 rs1 bmode1 bss tmr0 tmr1 tmr2 ts1 ddet dt1 dt2 tc2 ts2 dr2 rc2 td dt0 tc0 ddit ts0 ddet bmode0 rc0 dr0 gd gd rs2 rd 1 13 12 11 10 13 13 13 13 13 12 13 133 132 131 130 12 12 12 12 12 123 122 121 120 11 11 11 11 11 11 113 112 111 110 10 20 1 1 gd 1 omode gd tc gd tms tdi tdo reset 1 1 1 ddet gd ddet trst ddit emu 13 12 11 10 3 2 1 0 dsstmeod32 hc ddet hc ddit ddet hcioms hcms
rev a ADSST-MELODY-32 e5e pin number mnemonic 109 a21 110 bgh 111 bg 112 br 113 bms 11 ioms 11 ms0 11 ms1 11 ms2 11 ddet 11 ms3 120 c 121 wr 122 rd 123 d0 12 d1 12 d2 12 d3 12 ddit 12 d 12 gd 130 cout 131 ddet 132 ci 133 t 13 gd 13 d 13 d 13 d 13 d 13 d 10 d10 11 d11 12 d12 13 ddet 1 d13 p m 3 reset tdo tdi tms gd tc trst 0 gd 1 emu 2 ddit 3 opmode 0 1 2 3 0 ddet 1 2 3 gd 10 11 12 13 100 ddet 101 1 102 1 103 1 10 1 10 gd 10 1 10 1 10 20 p m 1 d1 2 d1 3 hd0 hd1 gd hd2 hd3 hd hd 10 hd 11 hd 12 hd 13 ddet 1 hd 1 hd10 1 gd 1 hd11 1 hd12 1 ddit 20 hd13 21 hd1 22 hd1 23 hd1 2 hcp 2 ddet 2 hc 2 hcms 2 hcioms 2 gd 30 he 31 hrd 32 hwr 33 gd 3 p0 3 p1 3 p2 p m 3 p3 3 p 3 p 0 ddet 1 p 2 p 3 tmr0 tmr1 tmr2 dt2 tc2 ts2 dr2 0 rc2 1 rs2 2 rd 3 td gd gd dt0 tc0 ddit ts0 0 dr0 1 rc0 2 rs0 3 ddet dt1 tc1 ts1 dr1 rc1 rs1 0 bmode0 1 bmode1 2 bpss pidescriptios tm32tpxm32 citc trst i citc trst u ddet gdx ddr210dt10p0 trst bmode0bmode1opmode bpsstctmstdi reset t
rev a ADSST-MELODY-32 e6e pin type function pf4/spi0sel2/ msel4 i/o/t programmable flags 4/spi0 slave select output 2 (when spi0 enabled)/multiplier select 4 (during boot) pf3/spi1sel1/ msel3 i/o/t programmable flags 3/spi1 slave select output 1(when spi0 enabled)/multiplier select 3 (during boot) pf2/spi0sel1/ msel2 i/o/t programmable flags 2/spi0 slave select output 1 (when spi0 enabled)/multiplier select 2 (during boot) pf1/spiss1/ msel1 i/o/t programmable flags 1/spi1 slave select input (when spi1 enabled)/multiplier select 1 (during boot) pf0/spiss0/ msel0 i/o/t programmable flags 0/spi0 slave select input (when spi0 enabled)/multiplier select 0 (during boot) rd ot exprs wr ot expws c i expr bms ot expbss ioms ot expioss ms3C0 ot expmss br ie xpbr bg oe xpbg bgh oe xpbgh hd10 iot hpmx d hd1 i hpmsbb hcp i hpcp hrd ih prs hwr ih pws hc o hpr he i hps cc hcms i hpimiio mbms hcioms i hpiioms ci i cioi0 t i oi1 bmode10 i bm10 opmode i om cout o co b p ss i ppbm rc10 iot sport10rc rc2sc1 iot sport2rcspi1sc rs10 iot sport10rs rs2mosi1 iot sport2rsspi1 mosid tc10 iot sport10tc tc2sc0 iot sport2tcspi0s c piuctios p t 210 ot expb d0 iot expds b d1p1 iot d11bexbp spi1se 1bex b spi1sso b exbspi1e d1p1 spi0se iot d11bexbp 1bexb spi0ssob exbspi0e d13p12 spi1se iot d131bexbp 13bexb spi1sso b exb spi1e d12p12 spi0se iot d121bexbp 12bexb spi0ssob exbspi0e d11p11 spi1se iot d111bexbp 11 bexb spi1ssob exb spi1e d10p10 spi0se iot d101bexbp 10 bex b spi0sso bexb spi0e dp spi1se iot d1bexbp bexbspi1 sso bex b spi1e dp spi0se iot d1bexbp bexbspi0 sso bex b spi0e p spi1se3d iot pspi1 ss o3spi0ed dsp ib pspi0se3 mse iot pspi0ss o3spi0em sb pspi1se2 mse iot pspi1ss o2spi0em sb
rev a ADSST-MELODY-32 e7e pin type function tfs1e0 i/o/t sport1e0 transmit frame sync tfs2/mosi0 i/o/t sport2 transmit frame sync/spi0 master-output, slave-input data dr1e0 i sport1e0 serial data receive dr2/miso1 i/o/t sport2 serial data receive/spi1 master-input, slave-output data dt1e0 o/t sport1e0 serial data transmit dt2/miso0 i/o/t sport2 serial data transmit/spi0 master-input, slave-output data tmr2e0 i/o/t timer output or capture rxd i uart serial receive data txd o uart serial transmit data reset i prrm32 x t reset tc i tctgp tg tms i tmstgu tms 20 ? () ? () trst i trtgr trst m32 trst 20 ? emu o estgm m32 emu 0 ? ( ) ( ) ( ) ? ( ) () () () ? ? ? ? ? ? ? ? ? ? ( )
rev a ADSST-MELODY-32 e8e all the algorithms are implemented in 32-bit precision. for example, with this implementation the performance of the dolby digital code exceeds class a requirements mandated by dolby labs. figure 3 shows the software architecture. input stream output stream algorithm decode library executive kernel figure 3. software architecture booting the melody 32 processor boots from an external eprom or flash memory. the code is automatically booted on power-up. depending upon the stream detected, the appropriate code module is loaded from memory. the flash required is 512 k ? ? ? ? ? ? ? ()
rev a ADSST-MELODY-32 e9e ? () () ? () ( ) ? () () ? ? ? ? ? ? ? ( ms3C0 p ? ( ioms p ? ( bms p x1 exms ext x ? ? ? ? ( ) () ( ) () () ()
rev a ADSST-MELODY-32 e10e table ii shows the id and priority at reset of each of the peripheral interrupts. to assign the peripheral interrupts a different priority, applications write the new priority to their corresponding control bits (determined by their id) in the i nterrupt priority control r egister. the peripheral interrupt?s position in the imask and irptl register and its vector address depend on its priority level, as shown in table i. because the imask and irptl r egisters are limited to 16 bits, any peripheral interrupts assigned a priority level of 11 are aliased to the lowest priority bit position (15) in these registers and share vector address 0x00 01e0. table ii. peripheral interrupts and priority at reset reset interrupt id priority slave dma/host port interface 0 0 sport0 receive 1 1 sport1 transmit 2 2 sport1 receive 3 3 sport1 transmit 4 4 sport2 receive/spi0 5 5 sport2 transmit/spi1 6 6 uart receive 7 7 uart transmit 8 8 timer a 9 9 timer b 10 10 timer c 11 11 programmable flag 0 (any pfx) 12 11 programmable flag 1 (any pfx) 13 11 memory dma port 14 11 interrupt routines can be nested, with higher priority interrupts taking precedence or processed sequentially. interrupts can be masked or unmasked with the imask register. individual interrupt requests are logically anded with the bits in imask; the highest priority unmasked interrupt is then selected. the emulation, power-down, and reset interrupts are nonmaskable with the imask register, but software can use the dis int instruction to mask the power-down interrupt. the interrupt control (icntl) register controls interrupt nesting and enables or disables interrupts globally. the general-purpose programmable flag (pfx) pins can be configured as outputs, can imple- ment software interrupts, and (as inputs) can implement hardware interrupts. programmable flag pin interrupts can be configured for l evel-sensitive, single edge-sensitive, or dual edge-sensitive operation. dma controller the melody 32 has a dma controller that supports automated data transfers with minimal overhead for the melody 32 core. cycle stealing dma transfers can occur between the melody 32?s internal memory and any of its dma-capable peripherals. additionally, dma transfers can be accomplished between any of the dma capable peripherals and external devices connected to the external memory interface. dma capable peripherals include the: ? ? ? ? () ( ) ( ) ( ) ( ) ( ? ) () () ( )
rev a ADSST-MELODY-32 e11e arbitration for dma bus access is needed. the i/o bus arbitration priority for dma bus access is outlined in table iii. table iii. i/o bus arbitration priority dma bus master arbitration priority sport0 receive dma 0?highest sport1 receive dma 1 sport2 receive dma 2 sport0 transmit dma 3 sport1 transmit dma 4 sport2 transmit dma 5 spi0 receive/transmit dma 6 spi1 receive/transmit dma 7 uart receive dma 8 uart transmit dma 9 host port dma 10 memory dma 11?lowest host port the host port is implemented using pf pins and is spi compat- ible. any host microcontroller can communicate with melody 32 using this port. the host can send commands and parameters and melody 32 can send status data using this port. this provides simplex bidirectional communication. melody 32 serial ports (sports) the melody 32 incorporates three complete synchronous serial ports (sport0, sport1, and sport2) for serial and multi- processor communications. the sports support the following features: ? ? ( ) ? ( ) ? () () ? ? ( ) ? () ( ) ( ) ( spissx spi m321spispixse1 m32spi tspi uspix e spi spiclockrate hclk spibaud =
rev a ADSST-MELODY-32 e12e in slave mode, the melody 32?s core performs the following sequence to set up the spi port to receive data from a master transmitter: 1. enables and configures the spi slave port to match the opera- tion parameters set up on the master (data size and transfer format) spi transmitter. 2. defines and generates a receive tcb in page 0 of memory space to interrupt at the end of the data transfer (optional in dma mode only). 3. enables the spi dma engine for a receive access (optional in dma mode only). 4. starts receiving the data on the appropriate spi sckx edges after receiving an spi chip select on an spissx input pin (reconfigured programmable flag pin) from a master. in dma mode only, reception continues until the spi dma word count transitions from 1 to 0. the melody 32?s core could continue, by queuing up the next command tcb. a slave mode transmit operation is similar, except the melody 32?s core specifies the data buffer in memory space from which to transmit data, generates and relinquishes control of the transmit tcb, and begins filling the spi port?s data buffer. if the spi con- troller isn?t ready on time to transmit, it can transmit a zero word. uart port the uart port provides a simplified uart interface to another peripheral or host. it performs full duplex, asynchronous transfers of serial data. options for the uart include support for 5e8 data bits; 1 or 2 stop bits; and none, even, or odd parity. the uart port supports two modes of operation: ? ( ) ? ( ) ? ( ) ? ? ( = ) uartclockrate hclk d = ? ? ? ? ( ) ? ( )
rev a ADSST-MELODY-32 e13e when the melody 32 is in power-down core mode, the melody 32 core clock is off, but the melody 32 retains the contents of the pipeline and keeps the pll running. the peripheral bus keeps running, letting the peripherals receive data. to enter p ower-down core mode, the melody 32 executes an idle instruction after performing the following tasks: enter a power-down interrupt service routine: 1. check for pending interrupts and i/o service routines 2. clear (= 0) the pdwn bit in the pllctl register 3. clear (= 0) the stopall bit in the pllctl register 4. set (= 1) the stopck bit in the pllctl register to exit power-down core mode, the melody 32 responds to an interrupt and after two cycles of latency, resumes executing instructions with the instruction after the idle. when the melody 32 is in power-down core/peripherals mode, the melody 32 core clock and peripheral bus clock are off, but the melody 32 keeps the pll running. the melody 32 does not retain the contents of the instruction pipeline. the peripheral bus is stopped, so the peripherals cannot receive data. to enter power-down core /peripherals mode, the melody 32 executes an idle instruction after performing the following tasks: enter a power-down interrupt service routine: 1. check for pending interrupts and i/o service routines 2. clear (= 0) the pdwn bit in the pllctl register 3. set (= 1) the stopall bit in the pllctl register to exit power-down core/peripherals mode, the melody 32 responds to a wake-up event and (after five to six cycles of latency) resumes executing instructions with the instruction after the idle. when the melody 32 is in power-down all mode, the melody 32 core clock, the peripheral clock, and the pll are all stopped. the melody 32 does not retain the contents of the instruction pipeline. the peripheral bus is stopped, so the peripherals cannot receive data. to enter power-down all mode, the melody 32 executes an idle instruction after performing the following tasks. enter a power-down interrupt service routine: 1. check for pending interrupts and i/o service routines 2. set (= 1) the pdwn bit in the pllctl register to exit power-down core/peripherals mode, the melody 32 responds to an interrupt and (after 500 cycles to restabilize the pll) resumes executing instructions with the instruction after the idle. clock signals the melody 32 can be clocked by a crystal oscillator or a buffered, shaped clock derived from an external clock oscillator. if a crystal oscillator is used, the crystal should be connected across the clkin and xtal pins, with two capacitors connected as shown in figure 5. capacitor values are dependent on crystal type and should be specified by the crystal manufacturer. a parallel-resonant, fun- damental frequency, microprocessor-grade crystal should be used for this configuration. if a buffered, shaped clock is used, this external clock connects to the melody 32?s clkin pin. clkin input cannot be halted, changed, or operated below the specified frequency during normal operation. this clock signal should be a ttl compatible signal. when an external clock is used, the xtal input must be left uncon- nected. the peripheral clock is supplied to the clkout pin. msel0 (pf0) msel1 (pf1) msel2 (pf2) msel3 (pf3) msel4 (pf4) msel5 (pf5) msel6 (pf6) df (pf7) bypass reset v dd v dd 12.288mhz xtal clkin clkout runtime pf pin i/o reset source ADSST-MELODY-32 the pull-up pull-down resistors on the msel, df, and bypass pins select the core clock ratio. here, the selection 51mhz and 32mhz input clock produce a 160mhz core clock. v dd v dd figure 5. external crystal connections all on-chip peripherals for the melody 32 operate at the rate set by the peripheral clock. the peripheral clock is either equal to the core clock rate or one-half the melody 32 core clock rate. this selec- tion is controlled by the iosel bit in the pllctl register. the maximum core clock is 160 mhz, and the maximum periph- eral clock is 100 mhz; the combination of the input clock and core/peripheral clock ratios may not exceed these limits. reset t reset m 32t reset reset i reset t dd p 100 reset o reset rsp t reset irc reset xs t w reset
rev a ADSST-MELODY-32 e14e after a hardware reset, the dsp?s uart transmits 0xff values (eight bits data, one start bit, one stop bit, no parity bit) until detecting the start of the first memory block. the uart boot routine is located in internal rom memory space and uses the top 16 locations of page 0 program memory and the top 272 locations of page 0 data memory. ? ( ) = ( ) = () = = ? ( ) ? = ( ) ( ) ( ) = + = + = + = + = = ( ) () ( ) ( ) ( ) ( ) ( ) ? () () ? () () ? ( ) () () ?
rev a ADSST-MELODY-32 e15e the external component of total power dissipation is caused by the switching of output pins. its magnitude depends on: number of output pins that switch during each cycle ( o ) the maximum frequency at which they can switch ( f ) their load capacitance ( c ) their voltage swing ( v dd ) and is calculated by the formula below: pocv f ext dd = ( ) ( ) ( ) () msx 10 10 20 10 00000w wr 1 10 0 10 0003w d 1 0 10 20 10 001w cout 1 10 0 10 0002w p et 00w ppp total ext int =+ p ext is from table vi p int is i ddint i ddint calculation shown below: i typical i idle i power down i ddint ddint typical ddint idle ddint pwrdwn = () + () + () ?? ? () = () = = ( ) = ( ) = = ( ) = ( ) =
rev a ADSST-MELODY-32 e16e output enable time output pins are considered to be enabled when they have made a transition from a high impedance state to when they start driv- ing. t he output enable time, t ena, is the interval from when a reference signal reaches a high or low voltage level to when the output has reached a specified high or low trip point, as shown in figure 7. if multiple pins (such as the databus) are enabled, the measurement value is that of the first pin to start driving. example system hold time calculation to determine the data output hold time in a particular system, first calculate t decay using the equation in the output disable time section. choose ev to be the difference between the adsst- melody-32?s output voltage and the input threshold for the device requiring the hold time. a typical ev will be 0.4 v. c l is the total bus capacitance (per data line), and i l is the total leakage or three- state current (per data line). the hold time will be t decay plus the minimum disable time (i.e., t datrwh for the write cycle). capacitive loading output delays and holds are based on standard capacitive loads: 50 pf on all pins (see figure 11). the delay and hold specifications given should be derated by a factor of 1.5 ns/50 pf for loads other than the nominal value of 50 pf. figure 10 and figure 11 show how output rise time varies with capacitance. these figures also show graphically how output delays and holds vary with load capacitance. note that this graph or derating does not apply to output disable delays; see the output disable time section. the graphs in these figures may not be linear outside the ranges shown. load capacitance e pf 40 050 rise and fall times e ns (10% e 90%) 100 150 200 250 30 0 10 20 rise time fa ll time figure 10. typical output rise time (10% e 90%, v ddext = minimum at maximum ambient operating temperature) vs. load capacitance environmental conditions the thermal characteristics in which the dsp is operating in flu ence performance. thermal characteristics the ADSST-MELODY-32 comes in a 144-lead lqfp package. it is specified for an ambient temperature (t amb ) as calculated using the formula that follows. test conditions the dsp is tested for output enable, disable, and hold time. output disable time output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage. the time for the voltage on the bus to decay by ev is dependent on the capacitive load, c l and the load current, i l . this decay time can be approximated by the equation below. t cv i decay l l = ? () () () ? () ( ) ( )
rev a ADSST-MELODY-32 e17e table vii. ( ) ( ) ( ) ( ) tt pd amb case ca =? t amb = ambient temperature (measured near top surface of package) pd = power dissipation in w (this value depends upon the specific application; a method for calculating pd is shown under power dissipation) ca = value from table vii for the lqfp package: =
rev a ADSST-MELODY-32 e18e club reverb the club reverb is an algorithm with a reverberation and smooth decay. parameters: delay music a music algorithm simulating a music hall. cinema a cinema-like surround sound is simulated using special filters. speaker equalization digital signal processing has many advantages over analog pro- cessing. digital processing allows the application of a wide range of mathematics. this provides more reliability, configurability, flexibility, and low noise susceptibility, resulting in very good performance in the digital system. loudspeakers are designed to have a uniform frequency response. but in case of the low cost, size, and the mechanical design constraints, the response of the speaker system is less uniform. in this case, in many audio systems, speaker equalization is performed to shape this response according to the listener. figure 13 shows the dual loudness curves for the melody 32 system. speaker equalization enables: ? ? ? ( )
rev a ADSST-MELODY-32 e19e frequency e hz 5 0 e20 10 1 10 2 relative amplitude e db 10 3 10 4 e5 e10 e15 10 0 figure 18. equalization effect e jazz surround frequency e hz 5 0 e20 10 1 10 2 relative amplitude e db 10 3 10 4 e5 e10 e15 10 0 figure 19. equalization effect e pop front and center frequency e hz 5 0 e20 10 1 10 2 relative amplitude e db 10 3 10 4 e5 e10 e15 10 0 figure 20. equalization effect e rock front frequency e hz 5 0 e20 10 1 10 2 relative amplitude e db 10 3 10 4 e5 e10 e15 10 0 figure 21. equalization effect e rock center equalizer equalizer equalizer equalizer equalizer equalizer equalizer equalizer left right center left surround right surround surround ba ck left surround ba ck right lfe (low frequency effects) left right center left surround right surround surround ba ck left surround ba ck right lfe (low frequency effects) volu me control figure 22. equalization effect
rev a ?0 c02776??/02(a) printed in u.s.a. ADSST-MELODY-32 outline dimensions 144-lead low profile quad flatpack [lqfp] (st-144) dimensions shown in millimeters 0.27 0.22 0.17 1 36 37 73 72 108 144 109 top view (pins down) 20.00 bsc sq 22.00 bsc sq 0.50 bsc seating plane 1.60 max 0.75 0.60 0.45 view a 7 3.5 0 1.45 1.40 1.35 0.15 0.05 0.08 max coplanarity view a rotated 90 ccw notes 1. the actual position of each lead is within 0.08 from its ideal position, when measured in the lateral direction 2. center dimensions are nominal compliant to jedec standards ms-026bfb revision history location page 7/02?ata sheet changed from rev. 0 to rev. a. edits to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 inserted new reference block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

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